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CALIFORNIA MICRO DEVICES
PACSZ1284
P/ActiveTM IEEE 1284 ECP/EPP Termination Network
Features
* 28-pin QSOP package * 17 filtering lines in a single package * In-system ESD protection to 30kV contact discharge per IEC 61000-4-2
Application
* Low cost Parallel Port Terminations and Filters for PCs and peripherals * Set-Top-Boxes for Internet Access
Product Description
California Micro Devices' filtering/ESD network provides an integrated parallel port solution in a single QSOP package. Enhanced high-speed parallel ports are used to provide communications between PC's, workstations, and external devices such as tape back-up drives, ZIP drives, printers, parallel port SCSI adapters, external LAN adapters, scanners, video capture, and other PC peripherals. These ports support bi-directional transfers to 2MB/sec. In addition, government EMC limits impose filtering requirements on the parallel port. The device provides a complete parallel port termination solution. It integrates the equivalent of 60 discrete components and is ideal for space critical applications. The pins of the device which connect to the parallel port are protected to 30kV contact discharge, well beyond Level 4 of the IEC 61000-4-2 specification. All other pins are ESD protected for contact discharges up to 8kV per IEC 61000-4-2. There are two available values for the pull-up resistor R1. The PACSZ1284-01 has R1 = 1k, and the PACSZ1284-02 has R1 = 2.2k. California Micro Devices' technology provides high reliability and low cost through manufacturing efficiency. California Micro Devices' solution is silicon-based and has the same reliability characteristics as today's integrated circuits.
SCHEMATIC CONFIGURATION
S TA N D A R D PA R T O R D E R I N G I N F O R M AT I O N
Package RC Code 01 02 Pins 28 28 Style QSOP QSOP Ordering Part Number Part Number PACSZ128401Q PACSZ128402Q Part Marking PACSZ128401Q PACSZ128402Q
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(c) 2000 California Micro Devices Corp. All rights reserved. 7/14/2000
C0970500
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
PACSZ1284
ABSOLUTE MAXIMUM RATINGS
Parameter VCC Voltage Input Voltage range, no clamping Temperature Storage: Operating Ambient Operating Junction Power D issipation per resistor Package Power D issipation Rating 5.5 - 0 .4 to 5 .5 - 4 0 to 1 5 0 0 to +7 0 0 to +1 2 5 0.1 1.0 W W Unit V V
oC
O P E R AT I N G C O N D I T I O N S ( u n l e s s s p e c i f i e d o t h e r w i s e )
Parameter VCC Voltage Ambient Temperature Rating 5.0 0 to +70 Unit V C
E L E C T R I C A L O P E R AT I N G C H A R A C T E R I S T I C S ( ov e r o p e r a t i n g c o n d i t i o n s u n l e s s s p e c i f i e d o t h e r wi s e )
Symbol R1, R2 C ILEAK VESDi VESD Parameter Resistance tolerance Capacitor tolerance Leagage current to ground ESD protection, input pins ESD protection, connector pins Clamping voltage under ESD discharge Conditions Measured at 25C Measured at 1MHz, 2.5V DC Measured at 5.5V, 25C Pins 3-7,9, 11, 13, 14, 2 IEC61000-4-2 specification Pins 1, 2, 3, 8, 10, 12, 15-19, 21, 23-28, IEC61000-4-2 specification (ESD applied to connector pin, measured at corresponding input pin) 8kV discharge, Human body model -8kV discharge, Human body model 8 30 Min -20 -20 1 Typ Max 20 20 10 Unit % % A kV kV
VCLAMP
8.3 -2.7
V V
Note 1: Pins 3-7, 9, 11, 13, and 14 typically connect to the I/O pins of the Super I/O chip. Note 2: Pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, and 23-28 typically connect to the Parallel Port Connector. Note 3: ESD voltage is applied between Input/Connector Pins and ground, one pin at a time (guaranteed by design and characterization).
S TA N D A R D VA L U E S
R1 () 1.0k 2.2k R2 () 33 33 C (pf) 150 150 RC Code 01 02
(c)2000 California Micro Devices Corp. All rights reserved.
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
7/14/2000
CALIFORNIA MICRO DEVICES
Application Information
The IEEE 1284 specification requires both termination and EMI filtering on a total of 17 lines. Basic filtering is provided through the presence of a capacitor on all signal lines. The filter capacitor is the junction capacitance of an ESD diode. The typical capacitance at a reverse voltage of 2.5V is 150pF. This diode capacitance is somewhat voltage dependent. See Figure 1.
PACSZ1284
Figure 2 shows the typical Insertion Loss graphs of the PACSZ1284 for Data and Strobe signals. The curves are dependent on the physical location of the filter elements with respect to the ground terminal of this device. These graphs are measured in a 50 Ohm environment on a Hewlett Packard HP 8753C Analyzer. The signal source is introduced at the resistor input and the output is measured at the corresponding protection diode. The actual pins measured are labeled in the graph. See Figure 2.
Typical Filter Insertion Loss For PACSZ1284 (S21 in dB, T = 25C)
Figure 1
The higher speed Data and Strobe lines (9 in total) require an additional series resistor termination for proper operation while the eight (8) Status lines do not. See Table 1.
FREQUENCY (MHz)
Signal Name
Data 1-- Data 8 Strobe Init AutoFeedXT Selection Ack Busy Paper Empty Select Fault
S e r i e s Te r m i n a t i o n
Yes Yes Not Required Not Required Not Required Not Required Not Required Not Required Not Required Not Required
Figure 2
Table 1
(c) 2000 California Micro Devices Corp. All rights reserved. 7/14/2000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3

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